1. Field of the Invention
The present invention relates to a semiconductor switch.
2. Description of the Related Art
In order to test whether or not a semiconductor device operates normally, or in order to identify defective parts, a semiconductor test apparatus (which will be referred to simply as the “test apparatus”, or otherwise as the “ATE: Automatic Test Equipment”) is employed. Typically, such a test apparatus provides an AC test and a DC test.
In the AC test, a test pattern is generated by means of a pattern generator and a timing generator. Furthermore, a driver generates a pattern signal (test signal) that corresponds to the test pattern, and supplies the pattern signal thus generated to a device under test (DUT). Upon reception of the pattern signal, the DUT performs predetermined signal processing, and outputs an output signal to the test apparatus. By means of a timing comparator, the test apparatus judges the signal level received from the DUT. By comparing the judgment result with an expected value, the test apparatus judges the quality of the functions of the DUT.
In the DC test operation, a DC test unit supplies a DC voltage or a current signal to the DUT, and the test apparatus tests the DC characteristics such as the input/output impedance of the DUT, the leak current thereof, and so forth.
In many cases, a driver, a timing comparator, and a PMU configured to perform a DC test operation are arranged on a board which is referred to as a pin card (pin electronics card), a digital module, or an interface card, and which is configured such that the board can be removed from the main unit of the test apparatus.
FIG. 1 is a diagram showing a typical configuration of such a pin card. FIG. 1 shows only one channel that corresponds to a given device pin. In practice, several hundreds through several thousands of channels are arranged in parallel.
An I/O terminal Pio of a pin card 200 is connected to a corresponding device pin of a DUT 1 via a cable and an unshown device chuck. The pin card 200 includes two switches (relays) SW1 and SW2, in addition to a driver DR, a timing comparator TCP, and a DC test unit PMU. The switches SW1 and SW2 are used to switch the test mode between the AC test mode and the DC test mode.
When the AC test operation is performed, the switch SW1 is turned on and the switch SW2 is turned off. In this state, the driver DR and the timing comparator TCP are connected to the DUT 1, and the DC test unit PMU is disconnected from the DUT 1.
Conversely, when the DC test operation is performed, the switch SW1 is turned off and the switch SW2 is turned on. In this state, the driver DR and the timing comparator TCP are disconnected from the DUT 1, and the DC test unit PMU is connected to the DUT 1.
In many cases, such a switch SW is configured as a semiconductor switch instead of being configured as a mechanical relay. FIG. 2 is a circuit diagram showing a semiconductor switch 80 investigated by the present inventors. The semiconductor switch 80 includes a transistor 82 and a bias circuit 84 that controls the voltage of a control electrode (gate) of the transistor 82. The transistor 82 is configured as an enhancement-type N-channel transistor. For example, the transistor 82 is configured as a MIS-HEMT (Metal Insulator Semiconductor-High Electron Mobility Transistor).
FIGS. 3A and 3B are diagrams each showing an example of the current/voltage characteristics of such a HEMT. The HEMT has a control electrode (gate) G, a first electrode E1, and a second electrode E2. Of the two electrodes, i.e., the first electrode and the second electrode, the electrode that is set to a higher electric potential will be referred to as the “drain D”, and the electrode that is set to a lower electric potential will be referred to as the “source”. The HEMT is configured as a device that is capable of controlling the on/off state of the drain/source current. When the gate/source voltage of the HEMT exceeds a predetermined threshold value VTH, the HEMT is turned on. FIG. 3A shows the current/voltage characteristics of a HEMT in a case in which it is configured as an enhancement-type HEMT. FIG. 3B is the current/voltage characteristics of a HEMT in a case in which it is configured as a depression-type HEMT.
Description will be made returning to FIG. 2. The bias circuit 84 receives the power supply voltages VDD and VSS, and controls the gate/source voltage VGS of the transistor 82 according to a control signal VCNT which is an instruction to turn on or otherwise turn off the transistor 82.
Specifically, when the control signal VCNT is set to a first level (e.g., high level), the bias circuit 84 applies, as the gate/source voltage of the transistor 82, a voltage that is higher than the threshold voltage VTH. When the control signal VCNT is set to a second level (e.g., low level), the bias circuit 84 applies, as the gate/source voltage of the transistor 82, a voltage (e.g., 0 V) that is lower than the threshold voltage VTH.
When the power supply voltages VDD and VSS are normally supplied to the bias circuit 84, the bias circuit 84 is capable of appropriately turning on and off the transistor 82 according to the control signal VCNT. However, when the power supply voltages VDD and VSS are not supplied (which will be referred to as the “no-power-supply state”), the output of the bias circuit 84 is set to a high-impedance state. In this state, the output voltage of the bias circuit 84, i.e., the gate voltage VG of the transistor 82, is fixedly set to 0 V (ground voltage) (or otherwise set to an indefinite value).
Description will be made regarding the semiconductor switch 80 shown in FIG. 2 assuming that the output terminal P2 is set to 0 V, a variable voltage VIN is input to the input terminal P1, and the HEMI has a threshold voltage VTH of 1 V.
When VIN>0 V (e.g., VIN=5 V), the electric potential (5 V) at the first electrode E1 is higher than the electric potential (0 V) at the second electrode E2. In this state, the first electrode E1 functions as a drain, and the second electrode E2 functions as a source. In this case, VGS, which is represented by VGS=VG−VS, is 0 V, and accordingly, Vas is lower than VTH. Thus, the transistor 82 is turned off.
Conversely, when VIN<0 V (e.g., VIN=−5 V), the electric potential (−5 V) at the first electrode E1 is lower than the electric potential (0 V) at the second electrode E2. In this state, the first electrode E1 functions as a source, and the second electrode E2 functions as a drain. In this case, VGS, which is represented by VGS=VG−VS, is 5 V, and accordingly, VGS>VTH holds true. Thus, the transistor 82 is turned on.
As described above, with the semiconductor switch 80 shown in FIG. 2, in the no-power-supply state, the on/off state depends on the electric potentials at the input terminal P1 and the output terminal P2, leading to instability of the on/off state. However, with the pin card 200 shown in FIG. 1, in the no-power-supply state, the switches SW1 and SW2 are preferably turned off. In addition to such a pin card 200, there are various kinds of known switches required to be turned off in the no-power-supply state.